RE: Clock Stretching...

From: Baltissen, GJPAA (Ruud) (
Date: 2004-02-10 07:21:18

Hallo Nick,

> Does everyone else read it the same way?


Hallo Rainer,

> Wasn't the problem with RDY that it needs up to 3 cycles to be
> acknowledged,

Those three cycles are needed because the VIC hasn't any idea what the CPU
is doing and therefor MUST insert them in case a IRQ is going on.

The CP/M-cartridge for example doesn't need it. The cart is activated by
setting a bit in a register that on its turn pulls the DMA-input of the
expansionport low. Assume that at that moment IRQ was triggered. The first
thing the 6510 does is pushing three bytes to the stack. But the actual
writing hasn't started yet so therefor the 6510 honours the status of RDY
and halts.

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