----- Original Message -----
From: "Rainer Buchty" <buchty@cs.tum.edu>
To: <cbm-hackers@cling.gu.se>
Sent: Thursday, September 20, 2001 5:58 PM
Subject: Re: VHDL description of the REC
> I need to stick to one PLD language and not switching between VHDL, Palasm
> and ABEL all the time.
>
> Rainer
And what about Altera-HDL (from Max+Plus) and Verilog ? :)
BTW - Xilinx released something interesting - Java HDL compiler, also
written in Java. Pentium VII required :)
Konrad
Message was sent through the cbm-hackers mailing list
Archive generated by hypermail 2.1.1.