> I think you've got too many elseif's in the "DMA transfer" (?) > ie > if rst='0' then > elsif rising'edge(dotclk) then > elsif falling'edge(dotclk) then Hell... How could I have overseen the point. Of course, processes must only have one clock. I need to stick to one PLD language and not switching between VHDL, Palasm and ABEL all the time. Rainer -- Rainer Buchty, LRR, Technical University of Munich Phone: +49 89 289-28401, Fax +49 89 289-28232, Room S3240 Message was sent through the cbm-hackers mailing list
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