Re: VHDL description of the REC

From: Rainer Buchty (
Date: 2001-09-20 18:36:08

> I'll try encapsulating them in a package and see if that makes the
> syntax checker happy, but if that was your intent shouldn't you have
> included a port mapping?

Only when I instantiate the design from the outside, e.g. from "c64.vhd",
there I obviously need the port mapping ... The packaging turns the
inbound component description into a "black box" to be imported into other

> I wasn't quibbling with the way you were doing it, just trying to
> figure out how you meant to express it.

As I stated in my previous mail: I expressed it wrongly... Need to chop
the process into two, one clocked by rising'edge, one by falling'edge (or
clock'event and clock='0/1' to be more portable).

> That's your first real mistake ;)

Assuming that people read the REC register documentation before? :)



Rainer Buchty, LRR, Technical University of Munich
Phone: +49 89 289-28401, Fax +49 89 289-28232, Room S3240

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