Re: DMA successes with Verilog

From: Jim Brain <brain_at_jbrain.com>
Date: Fri, 15 Jun 2018 22:52:55 -0500
Message-ID: <778c8c5e-b6c4-0094-cd94-d5d59637d89b@jbrain.com>
On 6/15/2018 10:42 PM, Mia Magnusson wrote:
>
> Or maybe wait for a write operation, we can be sure that a write is
> data and not code, and after a write the CPU will fetch the next
> instruction (with reservation for what happens on the stack in some
> cases?).
I think all writes are safe places to interrupt the CPU (a PSH would be 
just a known address sta)
> But that could on the other hand take some time as it's
> possible to write code that runs for a long time without any writes
> (especially in an idle loop).
THat was noted by Gideon as well.

Jim
Received on 2018-06-16 06:01:08

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