Re: DMA successes with Verilog

From: Mia Magnusson <mia_at_plea.se>
Date: Sat, 16 Jun 2018 05:42:26 +0200
Message-ID: <20180616054226.00005166@plea.se>
Den Thu, 14 Jun 2018 21:07:38 -0500 skrev Jim Brain <brain@jbrain.com>:
> On 6/14/2018 4:29 PM, Mia Magnusson wrote:
> >
> > Why does the badlines work while you supposedly cant DMA any time
> > you want? (Assuming DMA is synchronised to the clock)?
> DMA is sync with PHI.
> 
> Not sure your question, but badlines are when the VIC-II essentially 
> uses the CPU slice of the clock cycle for it's own use.  Because it
> is doing so, it's a badline, and neither the main CPU or any DMA
> activity can use that slice.

Well, I'm calling VIC bus activity "DMA" too. But I got an answer to my
question earlier up in this thread. (The PLA does special magic when
VIC does it's "badline" DMA, but the PLA doesen't do that when a
cartridge does DMA, and in some cases the end result can be that a
write operation takes place several times which would be bad if it's
some of the I/O registers).

> > Anyways if you really want to know what the CPU is doing you could
> > watch the buses. More than two accesses to concecutive addresses
> > means that it is fetching from program, i.e. instructions or
> > operands.
> I don't think that's true.  a piece of code that reads data from it's 
> own space would trigger the same rule.

You are correct, I'm wrong. But add that you first detect more than two
consecutive addresses and then 1-3 addresses that's not consecutive to
the first addresses, and then one address that is consecutive to the
first addresses. That can as I see it only be code with data at some
other place.

Or maybe wait for a write operation, we can be sure that a write is
data and not code, and after a write the CPU will fetch the next
instruction (with reservation for what happens on the stack in some
cases?). But that could on the other hand take some time as it's
possible to write code that runs for a long time without any writes
(especially in an idle loop).

> > Then
> > it would be easy to see when it accesses some place else, that must
> > be data. Backtrace the data bus a bit and then you can be sure
> > where that instruction started and where it will end.
> I have faith that if there were easier ways, Gideon would have found
> and implemented them.

I hope so too.


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Received on 2018-06-16 06:00:43

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