On 6/15/2018 10:46 PM, Mia Magnusson wrote: > There must be some reason for a VIC 20 to have a transceiver between > VIC+RAM and CPU+ROM+I/O+cartridge port. I think it's because on a write cycle, the lines go to output in the early part of the cycle, which would mess up teh VIC-I. THis issue bit me on the 6809 project, so it's somewhat relevant to current discussions. I decided to use the TSC line (tri state control) to move the 6809 off the bus, so I could share the memory with the main CPU (coprocessor card). What I found is that if TSC is high (which holds the address and data lines in tristate) up to the rise of E clock, the CPU would HALT for the cycle. And, due to the setup needs of the 63c09, you really had to move TSC low about 80nS before E rise or the condition persisted. IN the prototype, I got around the issue by letting the 63c09 have the bus for all of E | Q, which then meant I needed the latch main CPU reads from shared memory on the first half of the main CPU's clock cycle (when 63c09 E was low and 63c09's Q was low) and then send onto the main cpu during the E=1,Q=1 quarter cycle. Thus, for the newer design, I gave up on TSC use, and put 541's and a 245 on the address and data lines. That way, I can slide the cpu off the bus for the E=low half cycle, allowing the main CPU access to the memory, and not have to worry about internal TSC latching issues. Jim > -- Jim Brain brain@jbrain.com www.jbrain.comReceived on 2018-06-16 07:00:04
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