Re: DMA successes with Verilog

On 6/13/2018 11:36 AM, silverdr@wfmh.org.pl wrote:
>> On 2018-06-13, at 07:06, Jim Brain <brain@jbrain.com> wrote:
>>
>> In other news, I now have 64kB reads working and 64kB writes working.
> How does it go in terms of timing / cycles?

I've not put a real REU into the logic analyzer, but I assume it's the
same.  Any phi cycle where ba is high during the low half of the cycle
and we are wanting to perform a DMA activity is latched as phi goes high
  and if that is true, the code performs the DMA during the high half
cycle of PHI.  As the last PHI cycle goes low, the pointers are reloaded
  if needed, and the dma flag is reset.



I can see on the logic analyzer when badlines happen, and your transfer
speeds are still constrained by that fact.  But, the idea of
transferring a block of bytes coming from a PC looks relatively easy to
implement if the 64 requests the transfer.  The issue, as I understand
it, is if you want to surreptitiously DMA data into the running 64
memory map, since you don't know where the 6510 is in it's instruction
fetch/decode/action cycle, and pulling DMA low will corrupt CPU
activities in flight.



Gideon Z has a nice writeup on the issue.



Jim