Re: Strange 8255 behavior

Den Tue, 12 Jun 2018 23:57:54 +0200 skrev Michał Pleban
<lists@michau.name>:
> Mia Magnusson wrote:
> 
> > I would rather suggest using a really fast SRAM (fast compared to
> > the CPU clocks used on the 8088 and 6509) and just let both CPU's
> > use the same single adress/data interface on the SRAM.
> 
> That sounds waaaay more complicated than just placing a dual-port RAM
> between the CPUs. You would need to check how the 8088 accesses the
> RAM, and if there is any possibility to synchronize it with the 6509.
> It's not like a dual-6502 system when the CPUs can be placed in
> opposite phases, I suspect that the 8088 is much more complicated and
> does not fit easily into the 6502 access model. Or maybe you could do
> some abitration where one CPU is given priority and the second is
> placed in a wait state, but that's still lots of work.

Well, yes, it is way more work but dual port sram's are expensive
and/or hard to find, so if counting in 10+ 8088 boards it might be
worth the effort.

Even though the 8088 uses a whole bunch of it's clock ticks for each
bus cycle, you don't actually have to hog the bus on a fast sram for
the complete 8088 bus cycle. You just have to write to sram at some
point when the address and data to be written is available, and you
only have to present read data to the 8088 at the small time window
when the 8088 samples the data bus.

So it might not be that hard to sync them up anyway.

But by syncing the 18MHz dot clock to the 8088 CPU clock the risk of
hard to find race conditions are far lower I think.

> We even don't know whether the card can be overclocked to 18 MHz at
> this point.

The only problem I can come to think of is dram and various surrounding
chips on the B motherboard.


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