> On 2018-06-13, at 07:06, Jim Brain <brain@jbrain.com> wrote: > > In other news, I now have 64kB reads working and 64kB writes working. How does it go in terms of timing / cycles? > No compare or swap, as I will need to once again modify the state machine to add those. If there is interest, I can put my Verilog up somewhere. I am highly interested in things DMA for 6502 based systems. Although I've chosen VHDL as my development "platform" rather than Verilog - to my understanding the main concepts remain fully valid across the two. With DMA I basically need consecutive writes for one of my projects and am very curious how fast and in groups of how many bytes could this be done in a given time frame. -- SD! - http://e4aws.silverdr.com/Received on 2018-06-13 19:00:05
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