Den Wed, 13 Jun 2018 12:53:01 -0500 skrev Jim Brain <brain@jbrain.com>: > I can see on the logic analyzer when badlines happen, and your > transfer speeds are still constrained by that fact. But, the idea of > transferring a block of bytes coming from a PC looks relatively easy > to implement if the 64 requests the transfer. The issue, as I > understand it, is if you want to surreptitiously DMA data into the > running 64 memory map, since you don't know where the 6510 is in it's > instruction fetch/decode/action cycle, and pulling DMA low will > corrupt CPU activities in flight. Why does the badlines work while you supposedly cant DMA any time you want? (Assuming DMA is synchronised to the clock)? Anyways if you really want to know what the CPU is doing you could watch the buses. More than two accesses to concecutive addresses means that it is fetching from program, i.e. instructions or operands. Then it would be easy to see when it accesses some place else, that must be data. Backtrace the data bus a bit and then you can be sure where that instruction started and where it will end. -- (\_/) Copy the bunny to your mails to help (O.o) him achieve world domination. (> <) Come join the dark side. /_|_\ We have cookies.Received on 2018-06-15 00:00:04
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