Re: C65 on Ebay

Den Sun, 5 Nov 2017 12:34:43 +0000 skrev smf <smf@null.net>:
> On 05/11/2017 11:31, Mia Magnusson wrote:
> 
> > To make things more complicated, there is a mode where Agnus
> > switches hsync and vsync to inputs. That way you could atleast in
> > theory generate video modes with different resolutions like a 40Hz
> > mode with over 300 visible lines. I don't know if anyone has tried
> > this. It seems like this was ment to be used for genlocking but
> > then someone found out that it works better to just PLL the system
> > clock.
> 
> AFAIK that is how you have to genlock. Synchronising the system clock
> just gives you the correct pixel clock, you also have to send hsync
> and vsync reset pulses into the amiga so that it knows when the frame
> and lines start. I assume the copper list gets restarted as soon
> vsync is reset & that it detects which interlace field to display
> because of the relationship of vsync/hsync.

Well, you can use a PLL for the system clock oscillator and control the
PLL so sync *outputs* from the Amiga is in phase with sync from the
signal you genlock onto.
 
> I don't know if you can use it to generate custom video modes larger
> than the standard modes, but ECS came along and allowed you to
> generate whatever mode you wanted anyway.

Maybe sometime in a distant future I might try that :)

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