> On 2017-11-05, at 19:02, Mia Magnusson <mia@plea.se> wrote: > >> AFAIK that is how you have to genlock. Synchronising the system clock >> just gives you the correct pixel clock, you also have to send hsync >> and vsync reset pulses into the amiga so that it knows when the frame >> and lines start. I assume the copper list gets restarted as soon >> vsync is reset & that it detects which interlace field to display >> because of the relationship of vsync/hsync. > > Well, you can use a PLL for the system clock oscillator and control the > PLL so sync *outputs* from the Amiga is in phase with sync from the > signal you genlock onto. Theoretically looks like you could probably do this (and then constantly monitor for drifting and react), but the questions are: 1) why make it more difficult and expensive while at the same time potentially less reliable and slower to lock? 2) what for - if there is nobody willing to listen to those sync pulses anyway? >> I don't know if you can use it to generate custom video modes larger >> than the standard modes, but ECS came along and allowed you to >> generate whatever mode you wanted anyway. > > Maybe sometime in a distant future I might try that :) Let us know when you get some interesting results! :-) -- SD! - http://e4aws.silverdr.com/ Message was sent through the cbm-hackers mailing listReceived on 2017-11-05 20:00:43
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