On 12/27/2016 10:36 AM, Gerrit Heitsch wrote: > On 12/27/2016 11:56 AM, Michał Pleban wrote: >> >> 1. Have the CPLD check for reset vector access, that is, for a fetch >> from $FFFC immediately followed by a fetch from $FFFD. This will catch >> the reset sequence as well as JMP ($FFFC) which is also a kind of reset, >> but it will not catch other accesses to the vector like LDA $FFFC. > > Don't forget that CPU memory access is interleaved with VIC. So you > won't see an access to $FFFC immediatly followed by an access to > $FFFD, there will be at least one access to wherever inbetween. If > you're unlucky and catch a badline there will be more... > > In order to filter out the CPU accesses, you will have to also look at > AEC, RDY and PHI0. > > Gerrit > > > > Message was sent through the cbm-hackers mailing list I don't think that is correct. As I look at the schematic, I don't see where the VIC memory accesses would select the ROM IC via the PAL, and so can't you just gate on !CE (or !CE/!OE on larger ROMs) to ensure that only CPU accesses are watched? Jim Jim Brain brain@jbrain.com www.jbrain.com Message was sent through the cbm-hackers mailing listReceived on 2016-12-28 04:00:02
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