Re: Switchless ROMs

From: Gerrit Heitsch <>
Date: Wed, 28 Dec 2016 17:06:19 +0100
Message-ID: <>
On 12/28/2016 04:29 AM, Jim Brain wrote:
> On 12/27/2016 10:36 AM, Gerrit Heitsch wrote:
>> On 12/27/2016 11:56 AM, MichaƂ Pleban wrote:
>>> 1. Have the CPLD check for reset vector access, that is, for a fetch
>>> from $FFFC immediately followed by a fetch from $FFFD. This will catch
>>> the reset sequence as well as JMP ($FFFC) which is also a kind of reset,
>>> but it will not catch other accesses to the vector like LDA $FFFC.
>> Don't forget that CPU memory access is interleaved with VIC. So you
>> won't see an access to $FFFC immediatly followed by an access to
>> $FFFD, there will be at least one access to wherever inbetween. If
>> you're unlucky and catch a badline there will be more...
>> In order to filter out the CPU accesses, you will have to also look at
>> AEC, RDY and PHI0.
>>  Gerrit
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> I don't think that is correct.
> As I look at the schematic, I don't see where the VIC memory accesses
> would select the ROM IC via the PAL, and so can't you just gate on !CE
> (or !CE/!OE on larger ROMs) to ensure that only CPU accesses are watched?

You can do that, yes, since VIC will not access the KERNAL ROM. But you 
still need to take the possibility of a badline in the middle of the 
vector fetch into account.


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Received on 2016-12-28 17:01:47

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