On 12/27/2016 08:14 PM, Michał Pleban wrote: > Hello! > > Gerrit Heitsch wrote: > >> But since there is no RESET pin, >> any assertion of the CPU RESET pin will not phase VIC and it will >> continue with what it was doing. So there is a possibility that the CPU >> has just pulled the first byte of the RESET vector when VIC asserts RDY >> and stops the CPU for 43 cycles. > > OK, this is not good, but how likely is it to happen exactly between the > fetch from $FFFC and $FFFD? I guess not very much. If the probability is > in 0.x % range, I think the user could just reset the computer again in > such unlikely case. Of course the probability is small, but at least I don't like to ignore such edge cases. It usually means you're overlooking something else too. The circuit has to work flawlessly in all possible cases. Remember, VIC is not the only one who might grab the bus from the CPU, there are Expansionport cartridges that can do the same, for example the REU. The REC 8726 has a RESET pin, so this might not be a problem with a hard RESET. It could still be a problem with JMP ($FFFC) though. So, plain and simple, do NOT go by time elapsed between fetches from $FFFC and $FFFD alone. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2016-12-27 20:00:20
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