> On 2016-04-23, at 02:45, Mark McDougall <msmcdoug@iinet.net.au> wrote: > In short, yes. If you write VHDL or Verilog, you will be able to switch between the major vendors' devices without too many issues. Where they differ is in the clocks/PLL's and the on-chip memory, and how you synthesize them. The idea is to start with CPLD and implement some "non-clocked" logic first. Something like replacing big parts of the circuit(s) with one chip. For this I have the 5V chips from Altera. At some point though there will be a need for clocked stuff and RAM/ROM things. And here I have the XC3x00As from Xilinx. So at some point I'll probably need to move parts of the CPLD implemented stuff into FPGA, and moreover another vendor's one. > I'd suggest you look at one of the free/student versions of ModelSim if you want to avoid "vendor lock" as you put it. There were versions packed-in with older releases of Quartus, for example. IIUC there are also opensource/free version of simulators available which should be adequate for simulation. Someone mentioned these are "useless" for synthesis, but if you're only simulating they should be perfectly fine. Yes, thanks - downloading the free version of ModelSim now. Shall check that first. > I have several years of experience in FPGA design, in both VHDL and (some) Verilog. I can't overstate the usefulness of simulating your design, especially when starting out. No need to convince me on that! :-) > One of our early clients insisted on a full simulation test-bench for a sizeable project; we actually wrote several times more code for, and spent many more hours developing the testbench than the actual target design itself, and it was an invaluable lesson. Well, that's not uncommon in the software domain either. In many projects I had a situation where the feature had a hundred lines or so, while the tests for that feature went into four figure range. > FTR having worked with Altera & Xilinx, I much prefer the former, both the devices and the tools. So much so, I actively avoid Xilinx work these days. Ughh!! I also much prefer VHDL over Verilog, despite having a software background, though I'd concede that writing testbenches is much more efficient in Verilog! Thanks for your response - every little bit counts. -- SD! Message was sent through the cbm-hackers mailing listReceived on 2016-04-24 02:00:43
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