Hi again! After some hours of thinking, I seem more confused in this subject than ever :-(. The 6502 variant in the Plus/4 should act really strange. I mean, from the first point, it gets data from a data bus that is of half the speed that a 6502 would usually need. As we know, the 6502 clones do memory accesses just in one half of the clock cycle, when the clock signal is on high logical level. After that, the read byte is either decoded (if it was an instruction code) or treated as whatever part of the previously decoded instruction, in the second half of the clock cycle. Now, if one would - say - replace the above mentioned 6502 to one that runs at twice as fast, but keeping the previous system bus, the following would happen: either 1.) the 6502 would have twice as fast control signals and thus the whole matter won't work, or, 2.) the signal timing would remain the same, but, since the core runs twice the speed to the memory access, when the proc read the byte it just would run over the time it should have decoded the read byte. Since I don't believe that _any Commodore manufactured 6502 core proc would decode an instruction or do other tasks in no time (say, even if it's pipelined as seen in some procs), I must suppose that they did something like a work-around in the _computer, not in the proc itselves. The processor, unlike other manufacturer's processors, derives its internal timings by somehow itselves. These timings must not be derived from the nominal 1Mhz clock frequency, since these timings actually suppose a higher time resolution than 1Mhz (other processors, like Intel clones tend to derive these timings from the main clock; but there, the clock is used to be much higher - they can derive the controller signals, and they divide the clock, resulting in a much lower, about-1-Mhz instruction clock). So I must suppose that they have to be based on units like triggerable monostable multivibrators or so. This should be the reason why original 6502 procs used to be available in just 1,2,3 or 4Mhz versions (since the timings depend on internal timing components). Let's check this in the 8501s point of view. Let's suppose, it is a 2Mhz 6502 variant. Keeping in mind the things above, we should suspect that it has timing parameters of a real 2Mhz 6502. Sometimes we make this work @ about 1, sometimes @ about 2Mhz. Then what? Changing the base clock, if the control timings are derived from monostables, means no change in the control timings. The memory control timings, that's for sure in a 2Mhz 6502, are calculated for the 2Mhz operation. And must remain the same when we switch to 1Mhz mode. O.K. let's see what I suppose from these. The system bus in the Plus/4 should be timed really weird. Somebody should prove it; I think, all memory accesses on the bus should finish in just the _first_half of all memory cycles. What I'm referring here, is that in opposition to a C64, all memory accesses run twice as fast as they run in the C64, and each second bus cycle halfs must be unused, free. Let me make this bright from an other point of view: if we had a C64, and used this method, we would have the processor finish its memory operation in the first _half of its _memory_access:cycle (thus half the time it currently reads a memory byte), wait or do whatever until the clock signal drops, then the VIC would also perform its memory read in half its memory access time, then do whatever and wait until the clock rises. Hope this helps clearing what I mean. As this shows, changing to this scheme doesn't mean doubling the data bus performance (since, the timing is doubled but each second and fourth quarters are skipped). But needs faster RAM chips and other components. I'm not sure if the chips that were O.K. for the C64, would also work in the Plus/4. Maybe this is also the reason why the designers needed to generate an own clock for the ACIA (which is a much older component than the chips in the Plus/4). They had to generate Phi2 (by the FPLA) just to be able to communicate with the ACIA. My theory could be inaccurate. But finally, I think it shouldn't go on much different. (After checking the PHI0 against PHI2 diag again, I'd suppose that each _first and _third quarters of a single clock cycle should be skipped from memory operation (first half: 0, TED; second half: 1, CPU) and they should be fully done in Q2 and Q4. When twiee clock: the clock doubles, each CPU clock cycle corresponds to two memory cycles; the first is skipped as usual in 6502 systems (Q1) and the CPU performs its memory operation in the second cycle (high clk state) (Q2).) Well. This whole matter still haven't helped understanding GATE IN. I disassembled my computer. Tried to disconnect GATE IN. Nothing changed when I disconnected it. But it did when I shorted the input to GND: it broke the program I ran. a2000 sei lsr $ff06 lda #$00 x sta $ff19 jmp x This generates a running pattern on the black screen (since the TED puts a white pixel out whenever one writes the color registers). When I shorted the pin to GND, it wrote a 0 to the jmp instruction code ;-). That's all, have to go to sleep... L. - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail cbm-hackers-request@dot.tcm.hut.fi.
Archive generated by hypermail 2.1.1.