Re: 264 series questions

From: Levente Hársfalvi (
Date: 1999-10-03 19:58:46


> Maybe I will get more responses here. A while ago I asked on c.s.c about
> the strange GATE IN signal input on the 264 series CPU, the 7501/8501.
> Because I want to make a discrete replacement from a 6502, some '245
> drivers and a port chip, maybe a 6522 for the first experiments. But
> what does GATE IN do?

I don't know. But as maybe you've seen, the GATE IN is connected to the
TED's MUX output. MUX controls the DRAM address multiplexers (2x
74ls257); whenever MUX is low, the multiplexers select their A inputs,
else select B.

In the Plus/4, MUX goes high in somewhere the middle of each bus cycles,
_after RAS' and _before CAS' has dropped. Something like CAS' in the C64
(since CASRAM' is used for the DRAM chips' CAS' input instead).

With a more Plus/4 specific point of view, MUX oscillates at a constant
twiee clock frequency, going up in the middle and back in the end of
each bus cycles.

Unfortunately, I don't know for what it is used in the processor. It
must have something to do with the fact that the 8501s clock is doubled
sometimes, that's for sure. All in all, I don't know why the 8501 has to
be informed on the actual state of multiplexing. 

> One of the few Plus/4 resources mentions it as R/W
> GATE input, so I assume it has influence on the R/W output of the CPU.

Yes, that should be true. If you double the processor clock, the
processor is supposed to pull its R/W' output in write cycles twice as
fast as would with normal clock - thus try tell the DRAMs to accept the
written data _before they could accept it. In other words, these DRAMs
accept the WE' signal _after the RAS' has dropped, but _before 'CAS went
down. The bus expects the units to handle the control lines properly
('cos it actually doesn't know that a bus cycle is performed by whom, be
it the TED or the CPU, even the TED or the CPU multiple times in a row).
But the 6502 series CPU (with the particularly doubled clock) would
surely fail complying with that.

Should I suspect that GATE IN is used to delay the R/W' line output, in
write cycles, until MUX (or GATE IN) goes up?

> But why is it needed? Maybe because of the weird clock signals the TED
> feeds into the CPU? If that is all, a simple AND gate should be enough
> to do the same job. I really should have a look with an oscilloscope.

Well, that should be the best.

Please tell me if you succeeded substituting the 8501 with a bare 6502.
The 8501 is for sure the worst semiconductor part of the Plus/4 (as long
as we talk about the original CPU's manufactured in '84).


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