Re: 264 series questions

From: Nicolas Welte (
Date: 1999-10-04 12:58:09

Levente Hársfalvi wrote:
> I disassembled my computer. Tried to disconnect GATE IN. Nothing changed
> when I disconnected it. But it did when I shorted the input to GND: it
> broke the program I ran.

This gives much hope for getting away even without emulating that input

I will still have to think about the many ideas you presented, but I
want to add some additional thoughts right away:

According to the Plus/4 timing diagram, the CPU gets a Phi0 clock signal
which looks very different from a standard signal with 50% duty cycle if
in double clock mode. _Maybe_ some timing circuits in the 8501 are based
on the average clock frequency (which is about 1MHz in single clock
mode) and not on the length of the active cycle (which still is
equivalent to about 2MHz, even in single clock mode). _Maybe_ some
signals have to be tweaked with the GATE IN input because of this.

In a C128, which also has a slow and fast mode, it works quite
differently. The Phi0 signal has a proper 50% duty cycle in both clock
modes, and there is no special input or external circuitry to treat any
of the CPU output signals. But the CPU also doesn't have a Phi2 output,
just like the 8501. Who knows if this was done to save a pin for an
extra port bit or if the Phi2 output would be crap anyway because of the
strange input clocks. But then the 1571 drive can also switch between 1
and 2MHz without any problems, and it uses the 6502A Phi2 output. Hmmm.

BTW, how do the TED memory accesses work? I assume that since unlike the
VIC-II it gets all information from system memory and there is no extra
color memory, it must have more accesses to the memory than the VIC-II.
It should also be true that the TED memory clock always runs at about
2MHz and uses, speaking in quarters of a full single clock cycle, the
quarters Q1, Q2 and Q3 during active display, and only the quarters Q1
and Q3 in the retrace areas. So the CPU gets only quarter Q0 in single
clock mode and quarters Q0 and Q2 in double clock mode.

I also found what I think is the TED patent document on the net, but it
doesn't speak of the interfacing to the 8501 CPU :-( They only speak
about the 6510. 

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