Re: Verilog help appreciated

From: Mark McDougall <>
Date: Tue, 19 Nov 2013 08:00:51 +1100
Message-ID: <>
On 19/11/2013 3:00 AM, Nate Lawson wrote:

> The right way to observe this is to run it in simulation. Coming from a
> software background, I've found it useful to do my own drivers in C and
> interface with Verilog through its VPI interface. Then you can just send
> data in and read out or view the waveform without having to write more
> Verilog as the test bench.

Can't stress enough the utility in simulation.

Interesting approach with C. One of my first major designs involved the 
opencores PCI core which has a rather sizeable Verilog testbench. I was 
still honing my VHDL skills, with little exposure to Verilog, but found it 
far easier to write testbenches in Verilog than VHDL. So for a few years I 
was writing synthesisable code in VHDL and testbench code in Verilog! Then I 
decided to bite the bullet and do away with Verilog altogether, although it 
is handy to be able to at least read it.


|              Mark McDougall                | "Electrical Engineers do it
|  <>   |   with less resistance!"

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Received on 2013-11-18 22:00:07

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