Re: Verilog help appreciated

From: Nate Lawson <>
Date: Mon, 18 Nov 2013 13:23:42 -0800
Message-Id: <>
On Nov 18, 2013, at 1:00 PM, Mark McDougall wrote:

> On 19/11/2013 3:00 AM, Nate Lawson wrote:
>> The right way to observe this is to run it in simulation. Coming from a
>> software background, I've found it useful to do my own drivers in C and
>> interface with Verilog through its VPI interface. Then you can just send
>> data in and read out or view the waveform without having to write more
>> Verilog as the test bench.
> Can't stress enough the utility in simulation.
> Interesting approach with C. One of my first major designs involved the opencores PCI core which has a rather sizeable Verilog testbench. I was still honing my VHDL skills, with little exposure to Verilog, but found it far easier to write testbenches in Verilog than VHDL. So for a few years I was writing synthesisable code in VHDL and testbench code in Verilog! Then I decided to bite the bullet and do away with Verilog altogether, although it is handy to be able to at least read it.

The problem with both HDLs is that they are terrible for writing testbenches. I parse the Verilog into a tree of signals then use VPI to access them from a simple C interface. The C code can then read test vectors from files, run various events, and read out the results.

I like python more than C so I typically build a dynamic library plugin in C and then import it into python with CFFI. CFFI lets you import C files directly into python without translating interfaces with SWIG.

But this is all getting off-topic for this list.


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Received on 2013-11-18 22:01:53

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