RE: Verilog help appreciated

From: Bil Herd <>
Date: Mon, 18 Nov 2013 11:30:36 -0500
Message-ID: <>
Hi Jim,

One approach, which I use often as I don't like writing something already
done, would be to grab a Verilog UART from opencores, for example,osdvu
You can then create an interconnect sheet that calls the UART as a
submodule or sometimes I will create a schematic top sheet and place a
module that represents the HTL/HDL file.  You can use the UART as a drop
in or as a template for examples of all of the pieces.  I saw some
straight up 6551 UARTS also, some were in VHDL which is comparable but a
little more strict (some like that, some not so much)


-----Original Message-----
[] On Behalf Of Jim Brain
Sent: Monday, November 18, 2013 3:15 AM
Subject: Verilog help appreciated

Finally found some time to dip my toe into the Verilog waters, and could
use some help.  I am trying to convert an EAGLE schematic to some Xilinx
Verilog that I can synthesize onto a XC9572XL.  I have all of the pieces,
including a working build of the schematic, and all of the Xilinx Tooling,
a test CPLD PCB, etc., but I am not sure my Verilog is correct.

The circuit is a VIC-20 UART Cart, which needs an enable based on A[9:4]
comparison, a FLASH ROM connected to BLK5, and a read/write 8 bit bank
register.  I think I understand the simple FLASH signal "assigns", and the
comparator, but I'm glazing over at the register definition.  Or, I could
be way off on all three  My main concern is the HiZ on the register read
"assign" disrupting the "write" in the "always" block.

// seems like some of these need to be defined as wires or reg, but not
module main(
     input RESET,
     input [15:0] ADDR,
     inout [7:0] DATA,
      output [7:0] BANK,
     input CLK,
     input IO2,
     input IO3,
     output FLASH_CE,
     output FLASH_WE,
     output FLASH_OE,
     output UART_CE,
     input CART_EN,
     input FLASH_EN,
     input IO_SEL,
      input CR_W,
      input BLK5

comparator_6_bit addr_comp(ADDR[9:4], 0, ADDR_VALID);
register8        bank_reg(CLK, RESET, CART_EN & ADDR_VALID & !ADDR[3] &
!ADDR[2] & !ADDR[1] & !ADDR[0], CR_W, DATA, BANK);

assign IO_BANK = (IO_SEL) ? IO3 : IO2;
assign FLASH_CE = !(CART_EN & FLASH_EN & !BLK5);
assign FLASH_WE = (CR_W);
assign FLASH_OE = (!CR_W);

module register8( clock, reset, enable, read, data, regData);

input clock;
input reset;
input enable;
input read;
inout [7:0] data;
output [7:0] regData;
reg [7:0] regData;

// does the HiZ override the incoming data on a write?
assign data = (enable && read) ? regData : 8'bz;

always @ (posedge clock)
                 regData <= 0;
         else if(enable && !read)
              regData <= data;

module comparator_6_bit (
     input [5:0] a,
     input [5:0] b,
     output equal

   assign equal = (a == b);


Jim Brain

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Received on 2013-11-18 17:01:13

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