On Nov 18, 2013, at 12:14 AM, Jim Brain wrote: > Finally found some time to dip my toe into the Verilog waters, and could use some help. I am trying to convert an EAGLE schematic to some Xilinx Verilog that I can synthesize onto a XC9572XL. I have all of the pieces, including a working build of the schematic, and all of the Xilinx Tooling, a test CPLD PCB, etc., but I am not sure my Verilog is correct. > > The circuit is a VIC-20 UART Cart, which needs an enable based on A[9:4] comparison, a FLASH ROM connected to BLK5, and a read/write 8 bit bank register. I think I understand the simple FLASH signal "assigns", and the comparator, but I'm glazing over at the register definition. Or, I could be way off on all three My main concern is the HiZ on the register read "assign" disrupting the "write" in the "always" block. ... > module register8( clock, reset, enable, read, data, regData); > > input clock; > input reset; > input enable; > input read; > inout [7:0] data; > output [7:0] regData; > reg [7:0] regData; > > // does the HiZ override the incoming data on a write? > assign data = (enable && read) ? regData : 8'bz; Think of "assign" more like "connects". Since "data" is an inout definition, it's equivalent to a wire. So when enable and read go high, regData is connected to data. Otherwise, Z is connected to data. Logic values have strength levels implicitly, or you can override them and make them explicit. A 1 or 0 drive is higher than a z, though you could use a modifier like "strong0" or "pull1" to pull it to a specific level. http://www.asic-world.com/verilog/gate1.html The right way to observe this is to run it in simulation. Coming from a software background, I've found it useful to do my own drivers in C and interface with Verilog through its VPI interface. Then you can just send data in and read out or view the waveform without having to write more Verilog as the test bench. I typically use iverilog as the functional development interface for blocks, then move it into the actual environment in pieces. http://iverilog.icarus.com/ The IVI/Eclipse interface looks fun, though I've never used it. http://ivi.sourceforge.net/screenshots.html -Nate Message was sent through the cbm-hackers mailing listReceived on 2013-11-18 17:00:04
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