Re: Help with GAL needed

From: Michał Pleban <*lists_at_michau.name*> Date: Thu, 18 Apr 2013 15:59:18 +0200 Message-ID: <516FFC36.8030002@michau.name> · lists_at_michau.name

Hello!

Baltissen, GJPAA (Ruud) wrote:

> Please have a look at this:
> ...
> I just programmed two NAND gates. Now connect pin 19 with pin 4 and pin 18 with pin 3 and we have a fliflop IMHO. Or am I wrong?

Yes of course, you're right. I just wondered why are you doing this
instead of relying on the GAL's internal flip-flop :-) It would save you
input and output pins. Plus, as Dave already pointed out, the state of
this flip-flop is unknown on power up.

> As you say: "_IN_ the chip". And as I don't use the .D construct, I don't use these internal FFs (AFAIK).

Yes, correct.

> As you can see, I disagree with your conclusion but still thank you for your input because I still learned from it!

You're most welcome :-) Generally the idea of using a GAL to build NAND
gates to build a flip-flop from them is rather weird to me, but of
course it's perfectly valid.

Maybe that's the difference we were talking about privately, about the
CPLD preference? It looks like what you are trying to do is to step up
from TTL to CUPL, whereas when I design a circuit, I try to step down
from Verilog to CUPL :-)

Regards,
Michau.

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