RE: Help with GAL needed

Date: Thu, 18 Apr 2013 23:21:10 +0200
Message-ID: <001101ce3c7a$a6b04690$f410d3b0$@org>

I also tried this code:

library IEEE;

		PORT ( 
			clk  : in  STD_LOGIC;
			rdy  : in  STD_LOGIC;
			clk0 : out  STD_LOGIC);
	END rb;

architecture Behavioral of rb is
	SIGNAL clock_on_off : std_logic := '0'; 

	clk0 <= clk when clock_on_off = '1' else '1';
	PROCESS(clk, rdy)
		IF clk'EVENT AND clk = '0' THEN
			IF rdy = '1' THEN
				clock_on_off <= '1';
				clock_on_off <= '0';
			END IF;
		END IF;	
END Behavioral;

Seems ok on fpga + logic analyser but to way to compile for a GAL 
With lattice isp lever...


-----Message d'origine-----
De : [] De la part de Baltissen, GJPAA (Ruud)
Envoyé : jeudi 18 avril 2013 09:07
À : ''
Objet : Help with GAL needed

Hallo allemaal,
I have programmed several GALs so far but they all contained only lineair equations. I have designed a WAIT circuit for the 65816, which works fine, that is built using TTL gates:
As you can see, this schematic contains a flipflop. I use the 'old' CUPL.EXE to compile my equations. Please have a look at my equations for this schematic: 

	Name		ISA bus with 65816, GAL #3b;
	Device	G16V8AS;
	Designer	Ruud Baltissen;
	Date		2013-04-18;
	Revision	V0.1;

	Assembly	--;
	Company 	--;
	Location	--;
	Partno 	--;

/* Define Logic Operators */
	/* AND = &  */
	/* OR = #   */
	/* NOT = !  */     

/* Define Input Pins */
	pin  2 = CLK;
	pin  3 = RDY;

/* Define Output Pins */
	pin 12 = PHI0;		/* regulated CLK */
	pin 13 = FF1;
	pin 14 = FF2;

/* Boolean Equations */
	FF1  = !(!(!RDY & CLK) & FF2);
	FF2  = !(!(RDY & CLK) & FF1);
	PHI0 = !(!CLK & FF2);

CUPL compiled without any problem. But does it mean the above is good? I know it can be optimised/simplified, but as you can see the equations are a literally translation of the hardware. One part can be replaced by a single OR gate but then I would need at least three ICs in real life, now only two.

As you can see I reserved output pins for the flipflop. IMHO it cannot be done in another way. But I hope to be wrong in this case; the less output pins I need, the better.

Then there is the CLK input at pin 1. IMHO you only need it if you program (a part of) the GAL as counter. I know I haven't used any of the internal registers, but I don't know what CUPL made of it. So I'm not sure yet if it is needed.

Any help, suggestion, etc. is surely appreciated!

    / __|__
   / /  |_/     Groetjes, Ruud
   \ \__|_\

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Received on 2013-04-18 22:00:09

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