6502 bus timing

From: Michał Pleban <lists_at_michau.name>
Date: Tue, 24 Apr 2012 17:04:40 +0200
Message-ID: <4F96C108.80708@michau.name>

I have started examining the timing characteristics of the 6502 bus to 
understand how it interfaces with peripherals, so that I might model 
them correctly in Verilog :-)

I found some documentation here:

 From what I was able to decode from the timing diagrams, it seems to me 
that when reading from the peripheral, it is required to post data from 
its internal registers to the data bus on _raising_ edge of PHI2, 
whereas during writing to the peripheral, it should record the data from 
the data bus to its internal registers on _falling_ edge of PHI2. Is 
that correct assumption?


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