Hello! I have started examining the timing characteristics of the 6502 bus to understand how it interfaces with peripherals, so that I might model them correctly in Verilog :-) I found some documentation here: http://arlet.home.xs4all.nl/mcs6500_family_hardware_manual.pdf From what I was able to decode from the timing diagrams, it seems to me that when reading from the peripheral, it is required to post data from its internal registers to the data bus on _raising_ edge of PHI2, whereas during writing to the peripheral, it should record the data from the data bus to its internal registers on _falling_ edge of PHI2. Is that correct assumption? Regards, Michau. Message was sent through the cbm-hackers mailing listReceived on 2012-04-24 16:00:14
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