Hi Guys, A few things that came to mind: 1. The simplest solution would (as has already been said) to utilise some 'real' INTEL chips (e.g. 8088, 8259A etc.) and to put the majority of the 74LS devices into a 5V-tolerant CPLD. I would then use a separate CPLD to host the 6525/6526 combo (as these chips appear to be intertwined with each other and it would appear to be silly to implement the two separate chips in two CPLDs). As the lead technical engineer responsible for delivering a multi-million dollar remanufacturing project for a load of INTEL 8085, 8035, 8086 and 80286 cards, I have contact with the company that bought the IPR and all of INTELs stock of chips and silicon wafers many years ago when INTEL went on to bigger and better things. Once I place an order with the company I may be able to have access to 'samples' at very reasonable prices... I was having a look at the schematics I found on zimmers.net for the 8088 card last night and noticed a number of errors and deficiencies that would cause potential problems if the CPLD was implemented from them. For example - There are no pull-up resistors to the input of U10A when U8 is tristated. This will cause the inputs to U10A to float around. The TOD input to U15 (6526) is connected to U3 IR2 (8259A) - but both of these signals are inputs and there is no driving signal! Some of the pins on U2 (8284) appear to be floating. Some of the inputs to the unused gates on the TTL chips appear to be floating - this is bad practice. There are numerous other issues I have also found. Whilst looking around on the web this afternoon I came across two other schematic diagrams for the 8088 card (one on Ruud's website and one on vintagecomputer). Both of these schematics appear to not contain the issues I found on the schematic I printed out yesterday. My suggestion, therefore, is to print out all three schematics and to cross-check them with each other and find out which two agree with each other! I also came across an issue associated with data bus termination - or lack of - stating that the addition of 10 kOhm pull-up and pull-down resistors on the data bus cured some unreliability issues. Any redesign should incorporate any known bugfixes. 2. I also found a disassembly of the 8088s EPROM on zimmers.net. This appears to have been disassembled using an automated software tool which assumes that the image is for an IBM PC. The automated comments for the port access appear to assume that there is a DMA chip at I/O address 0 with an 8259 at address 20 (standard PC configuration). This is clearly not the case from the schematics. I have found a full-blown source code listing of the EPROM on vintagecomputer.net which makes much more sense than the disassembly. This EPROM does not contain what I would have thought of as a BIOS (e.g. for CP/M86) but appears to be a very slimmed-down bootstrap or set of interface routines to the host processor. The disassembly code I commented last night leads me to believe that the EPROM only uses a very small fraction of the 8259/6525/6526 functionality - so this is good news for CPLDing them. However, I also believe that other software is downloaded from the host processor to the 8088 which will probably do 'bit twiddling' on the hardware to implement functionality that is not coded in the EPROM - so analysing the EPROM code for the functionality of the peripheral chips may not identify what is actually required. For example, the TOD functionality of the 6526 is clearly used as someone has gone to the trouble of wiring up the TOD input - this feature is not activated from within the EPROM. The 6526 also appears to generate interrupts as the IRQ pin is wired. So the question is do we go for a minimal emulation of the 6525/6526 and expand it as we find functionality that is used that we have not implemented or do we go for a full-blown emulation and find that there is unused functionality - or do we just implement what appears easy and leave the rest for later? The EPROM code appears to also do 'strange' things. For instance, the Stack Pointer (SP) is initialised when reset - but not the Stack Segment (SS) as I would have expected. The default is for SS to be initialised to 0 on a reset. Interrupts are clearly used by the EPROM code - but I have not yet found anywhere where the 8088 interrupt vectors are actually initialised (unless this is initially done by the host processor). I have found some code in the EPROM which does play with the interrupt vectors - but this only seems to be executed later on once an interrupt has already occured. I will print out the source code listing from vintagecomputers.net tomorrow and have a read - it may shed some more light on this issue. 3. I would be hesitant to use VHDL/VERILOG implementations of the more complex INTEL chips. Having dug out my documentation on the 8284 and 8288 I agree that these are implementable in a CPLD/FPGA quite easily - especially given that most of the options for these chips are deconfigured by the pin strapping. I am used to fairly complex INTEL MULTIBUS boards which utilise much more of the functionality of these chips. The 8259 and 8088 are somewhat different. I have the VHDL code for both the 8259 and the 8088 somewhere - but I have never used them yet. My experience with software emulations leads me to believe that the products that have been engineered correctly, appear to have been thoroughly tested and come with reasonable documentation are not free but commercial. Most of the free implementations (not all) have been implemented to a degree but usually contain some simplifications (never documented) and a good smattering of bugs. These problems are usually compounded by lack of documentation as to where the originating source for the implementation actually came from. I developed an 80x86 simulator myself for a power station operator training simulator and had to cross-check multiple sources of documentation to find (and eliminate) genuine and deliberate mistakes. I then had to back this up by extensive testing of a 'real' 8086 and 80286 processor and then I could start coding... My experience of VHDL code is not much different. As I have said, there are some exceptions - but you have to look hard for them and have no means of adequately knowing how good they are until you use them and find they don't work as expected. 4. It would, however, be an interesting project to try and cram the whole lot into an FPGA with a few external chips for the bus buffers etc. !!! I'm a Xilinx/VHDL man - but that is only because the projects I have done in the past required features that Xilinx chips did and Altera didn't at the time. That is not the case anymore and I was looking at an Altera Stratix II the other day for a project (which has now fallen by the wayside though). I wouldn't go back to schematic capture now I have become proficient in VHDL (except, perhaps, for very small projects). Dave > Message Received: Apr 23 2012, 11:19 PM > From: "Michał Pleban" > To: email@example.com > Cc: > Subject: Re: FPGA (was: 6809 / 6702 puzzle) > > Hello! > > Bil Herd wrote: > > > The 6525 would be very straight forward, you could also do it using a > > schematic as entry as it's latches and buffers. > > The tools are all free, I switched from Xylinx to Altera many years ago, and > > the there are relatively cheap dev boards, from $70-$200 that can have a > > general purpose I/O breakout. > > Yes, I worked with Altera chips back at the university (that was > somewhere around 2004). > > Downloading Quartus software right now ;-) > > Regards, > Michau. > > > Message was sent through the cbm-hackers mailing list > Message was sent through the cbm-hackers mailing listReceived on 2012-04-24 16:00:28
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