RE: 6502 bus timing

From: Baltissen, GJPAA (Ruud) <ruud.baltissen_at_apg.nl>
Date: Wed, 25 Apr 2012 07:31:45 +0200
Message-ID: <219DEB1536CDE04E98DDD8620CA8CD68275CCF@winsv293.office01.internalcorp.net>
Hallo Micha,
 

> it is required to post data from its internal registers to
> the data bus on _raising_ edge of PHI2,

No, it is the address that should valid and stable on the rising edge. I was told that that is needed for the 6522 for example, maybe other 65xx ICs as well? That's why you need a trick to connect the 6522 to a C64.


> it should record the data from the data bus to its internal
> registers on _falling_ edge of PHI2. Is that correct assumption?

Correct.


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