RE: 6502 bus timing

From: Bil Herd <>
Date: Tue, 24 Apr 2012 15:39:23 -0400
Message-ID: <>
Yes, in a non-shared bus (no VIC chip) the general logic is address and R/W
valid on Rising edge of PHI and Data is valid on the Falling for either
reads or writes. If you use PHI as enable for an address decoder you can get
a valid single-event strobe since the address is valid before Phi and stays
valid till after.

The touchiest spec in the '02 family is the TDH spec, Time Data Hold and it’s
the amount of time data has to stick around after PHI ends.  This is where
faster parts hurt as faster parts let go faster.  The 02' also doesn’t leave
it's data out long so we used to use PHI0 instead of PHI2 for external
latching/gating.  The one timing spec in the TED family that we knowingly
violated was the TDH to the 6551, the margin is -3ns under worst case if I
remember correctly.

-----Original Message-----
[] On Behalf Of Michal Pleban
Sent: Tuesday, April 24, 2012 11:05 AM
Subject: 6502 bus timing


I have started examining the timing characteristics of the 6502 bus to
understand how it interfaces with peripherals, so that I might model them
correctly in Verilog :-)

I found some documentation here:

 From what I was able to decode from the timing diagrams, it seems to me
that when reading from the peripheral, it is required to post data from its
internal registers to the data bus on _raising_ edge of PHI2, whereas during
writing to the peripheral, it should record the data from the data bus to
its internal registers on _falling_ edge of PHI2. Is that correct


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Received on 2012-04-24 20:00:43

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