Re: on-chip flags (was: TED badlines, how do they work?)

From: Hársfalvi Levente <>
Date: Sat, 03 Sep 2011 19:14:13 +0200
Message-ID: <>
On 2011-09-03 14:24, Segher Boessenkool wrote:

> The way the RAM is written would make this automatic: when you write
> to the RAM, the drivers (coming from the data bus) overpower the coupled
> inverters in the selected bit cell; when you're not writing, they don't,
> and the bit cell keeps its value (the reading circuitry doesn't destroy
> the stored value, like with DRAM).
> So it's really easy to write only one byte of a 16-bit word: simply do
> not drive the bitlines of the other byte.

Speaking of sram cells... You can possibly light some clue on a small
detail that I couldn' have understood so far (...and you couldn't, it
might still be a warning about what's likely to be seen somewhere in the

As you say, the sram cells generally don't lose their content (because,
as I get it, they're built up like a classic, bistable sram cell, ie.
from two inverters).

One would suppose, flags must be implemented in a similar fashion ( some
bistable). Problem is: there are cases when that assumption seems to be
incorrect, some flags in the TED do indeed lose content if unaccessed.

For example, it's known that the TED sound timers can be locked up. In
short, there is a 10-bit timer for each sound generators. (...most
probably multiplexed; at least, the PWM output on the sndout pin, and
also some cycle-exact test routines do suggest that). The 10-bit freq
register is in fact a reload value for the timer. Reload happens when
the incremented value of the timer is $03ff. Upon timer reload, the
timer is overwritten by the reload value, an external signal raised, and
a T-flip-flop toggled - this T flip-flop is in turn the sound (square
wave) output itself, and also the clock for the noise generator.
...Now, if someone sets the reload register to $03fe, the timer locks
up; for each cycle, the timer increments the value, whose result is
always $03ff ie. the "reload" condition/output would be always true, and
no edges would toggle the T flip-flop anymore. This is all proven by
"practice", it does work (locking the timer up will cause the T
flip-flop to stop, by test it's possible to slow the noise generator
down this way which is otherwise impossible, etc.).

Odd thing is: one'd think, the T flip-flop keeps its state forever, once
the timer was locked up. Well, that's not the case. It'd slowly fade to
"1" state from "0" (if it was 0) in some 100 milliseconds. One can even
observe the process by digitizing the sound output (...note that the
state of the bit is always reproduced on the sound output, once sound
volume is nonzero, and the respective sound channel is enabled). It's
definitely an "analog" fadeout, one can observe a lot of digital noise
in the sound output, which is presumably picked up when the voltage
output of the flip-flop is nearing the next gate's digital input level

This is not the single example of such effect - something similar can be
experienced with the timers. The timers stop, once their low byte is
written. If they're kept in that state, they'd restart counting some
unpredictably long (~=some 100ms) time later, after having also
signalled an IRQ.

The question is - how could they have possibly implemented these
flip-flops, if they are not bistable cells? And if they're bistable
cells, how/why could they still lose their state?...


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Received on 2011-09-03 18:00:08

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