Re: TED badlines, how do they work?

>>  From that picture, I'm pretty sure it is a single 16x40 RAM.
>
> Looks like that to me too, but TED only has an 8 Bit data bus so  
> there must be a way to select upper and lower half of the RAM.

The way the RAM is written would make this automatic: when you write
to the RAM, the drivers (coming from the data bus) overpower the coupled
inverters in the selected bit cell; when you're not writing, they don't,
and the bit cell keeps its value (the reading circuitry doesn't destroy
the stored value, like with DRAM).

So it's really easy to write only one byte of a 16-bit word: simply do
not drive the bitlines of the other byte.

I don't see how the timing with two badlines can work, unless the RAM
can read and write the old and the new value at the same time.  Or maybe
that's interleaved, hrm...  While reading the bit pattern for char N on
a text line from memory, read the character pointer and attr for char  
N+1
from the SRAM; on the next memory clock, write either the char pointer
or the attr from memory to the RAM.  That makes everything completely
symmetric between char pointer and attr (the only difference is what
side is written); it requires the SRAM to be run at 2MHz (the VIC-II
runs it at 1MHz).

>> It seems to the right of it is the X and Y decoders; and to the right
>> of that are various registers to do with X and Y (Y on top, X at  
>> bottom
>> -- 9 resp. 10 bits).
>
> Still, VIC-II had about the same amount of logic but needed a lot  
> of space for the sprite logic. Ok, TED also has the sound  
> generator, keyboard port and chipset signal generation, but still.

It's hard to tell, but the TED is only about half the size of the VIC-II
as far as I can tell.  About a third or a quarter of that real estate
is taken by the sound and timer logic (again, hard to see for sure).

Need better pics :-)


Segher


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