Re: on-chip flags (was: TED badlines, how do they work?)

From: Segher Boessenkool <>
Date: Sun, 4 Sep 2011 10:55:15 +0200
Message-Id: <>
>> The way the RAM is written would make this automatic: when you write
>> to the RAM, the drivers (coming from the data bus) overpower the  
>> coupled
>> inverters in the selected bit cell; when you're not writing, they  
>> don't,
>> and the bit cell keeps its value (the reading circuitry doesn't  
>> destroy
>> the stored value, like with DRAM).
>> So it's really easy to write only one byte of a 16-bit word:  
>> simply do
>> not drive the bitlines of the other byte.
> Speaking of sram cells... You can possibly light some clue on a small
> detail that I couldn' have understood so far (...and you couldn't, it
> might still be a warning about what's likely to be seen somewhere  
> in the
> TED).
> As you say, the sram cells generally don't lose their content  
> (because,
> as I get it, they're built up like a classic, bistable sram cell, ie.
> from two inverters).

The SRAM is rather special: those two inverters are always feeding back
into each other, so you have to drive strongly to change the value  
and in fact, it drives both sides at the same time (in opposite  
because it is so much easier to drive strongly to 0 than to 1, in NMOS.

Usual register cells are made of two inverters in a feedback loop,  
but with
a switch (a pass transistor) in the loop so it can be broken when a  
new value
is written.  Usually that switch is just driven by a clock phase (so the
loop is broken more often than necessary, but simpler logic).

> One would suppose, flags must be implemented in a similar fashion  
> ( some
> bistable). Problem is: there are cases when that assumption seems  
> to be
> incorrect, some flags in the TED do indeed lose content if unaccessed.

I'm not sure what you mean with "flag", I'll assume you mean "whatever
that stores something" :-)

> For example, it's known that the TED sound timers can be locked up. In
> short, there is a 10-bit timer for each sound generators. (...most
> probably multiplexed; at least, the PWM output on the sndout pin, and
> also some cycle-exact test routines do suggest that). The 10-bit freq
> register is in fact a reload value for the timer. Reload happens when
> the incremented value of the timer is $03ff. Upon timer reload, the
> timer is overwritten by the reload value, an external signal  
> raised, and
> a T-flip-flop toggled - this T flip-flop is in turn the sound (square
> wave) output itself, and also the clock for the noise generator.
> ...Now, if someone sets the reload register to $03fe, the timer locks
> up; for each cycle, the timer increments the value, whose result is
> always $03ff ie. the "reload" condition/output would be always  
> true, and
> no edges would toggle the T flip-flop anymore. This is all proven by
> "practice", it does work (locking the timer up will cause the T
> flip-flop to stop, by test it's possible to slow the noise generator
> down this way which is otherwise impossible, etc.).
> Odd thing is: one'd think, the T flip-flop keeps its state forever,  
> once
> the timer was locked up. Well, that's not the case.

I bet that's because there is no T flip-flop, but some other (simpler)
circuit that behaves similarly.

> It'd slowly fade to
> "1" state from "0" (if it was 0) in some 100 milliseconds. One can  
> even
> observe the process by digitizing the sound output (...note that the
> state of the bit is always reproduced on the sound output, once sound
> volume is nonzero, and the respective sound channel is enabled). It's
> definitely an "analog" fadeout, one can observe a lot of digital noise
> in the sound output, which is presumably picked up when the voltage
> output of the flip-flop is nearing the next gate's digital input level
> threshold.
> This is not the single example of such effect - something similar  
> can be
> experienced with the timers. The timers stop, once their low byte is
> written. If they're kept in that state, they'd restart counting some
> unpredictably long (~=some 100ms) time later, after having also
> signalled an IRQ.

This one is documented in the datasheet actually (it says you should  
the high byte no later than 125us after writing the low byte).

> The question is - how could they have possibly implemented these
> flip-flops, if they are not bistable cells?

Dynamic (i.e. clocked) latches.  Values are stored as charge on  
(the input gate of an inverter pulldown, usually).  That charge will  
leak away if you don't refresh it.

> And if they're bistable
> cells, how/why could they still lose their state?...

A latch made of two cross-coupled NOR gates is bigger, and it becomes  
a lot
bigger if you want it to behave nicely (have a single input instead  
of set/
reset inputs, have an input enable signal, etc.)

Almost everything in NMOS circuits is dynamic logic: it is smaller,  
and it doesn't take much more power than static logic (it can even  
take less).


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Received on 2011-09-04 09:00:23

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