Re: petSD project page

From: Jim Brain <>
Date: Mon, 13 Jun 2011 21:47:44 -0500
Message-ID: <>
On 6/8/2011 9:18 PM, Ethan Dicks wrote:
> The 644P has 4 KB of on-board RAM, the 1284P has 16 KB, so I can see
> how buffer management could be an issue.
Over the years, there's been lots of effort to reduce RAM requirements 
in sd2iec (I helped a bit in the FAT library), but the code does contain 
conditional compilation as to buffer space per target architecture.  4kB 
RAM parts are compiled with a different number of buffers than 8kB RAM 

I do though, echo recommendations to use M1284 or 128kB+ parts for new 
designs, unless doing strictly hobbyist one-offs.

I have pledged many years ago to bring uIEEE to fruition, and thus I am 
committed to a commercial offering.  I have started updating my HW 
design, but I do want to add one thing before sending it onto the next 

Nils and Thomas Winkler have both noted the lack of an ATN ACK circuit.  
I know Nils notes it would add cost and potentially error, but a number 
of Classic Computer folks would love to have an generic IEEE488 option, 
and I'd prefer to at least see if a suitable low cost ACK could be added 
to the design.

Yes, I know (and have) the IEEE drive versions of the schematic with the 
requisite logic.  THe current logic looks to require a couple '00 and 3 
'02 gates, along with a potential inverter for ATN (if a '14 is 
initially used to invert it).  I'm wondering if someone is interested in 
simplify that logic to the bare necessity (More IO from the uC can be 
used to bypass non timing critical gates in the original design, for 
example).  If so, I'd love to include the simplified logic into the PCB 
design.  I'd love to get it down to a single gate type.


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Received on 2011-06-14 03:00:14

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