From: Scott McDonnell (netsamurai_at_comcast.net)
Date: 2007-04-08 08:24:48
Pasi, 512 cycles, because of the nyquist rate (at least 2x the max desired sample frequency), perhaps? Yep, this is how I remember it working. I was using a 555 timer and a counter to emulate the SID pot inputs. I believe this is method is called a "dual slope integrating ADC." RC time constants are very predictable. The only reason I still hold some doubt about this is that the paddles use 5V, the resistor changes the amount of time it takes for the cap to reach 63% of 5V. If you input say 2V, it will never reach 63% of 5V. The resistor never changes the voltage, just the current (or charge rate of the cap.) So the "decision level" you mention below would never really be satisfied. I am certainly not saying Jim is incorrect here (I accidentally responded directly to him, not the list) because PWM IS meant to control current. The voltage is always constant, it is just switched on and off at a varying duty cycle and frequency. Basically two solutions to the same problem, which would depend on the application. If a micro with PWM is being used, I would recommend that for sure. If the 0-5V source is just analog though, it might need the transistor approach. You mentioned that you had tried digitizing audio. Well, according to the specs, you would get max 800 hertz (1MHZ/512 cycles)/2. Of course this would be even less because of the processing time itself (actually grabbing the sample and storing it with code.) Probably not very practical as you would want about 2KHZ at least for speech. Might work for some slower signals, of course. I am still holding out. I think this has peaked my curiousity enough to dig out my equipment and do some experiments. Scott M. -----Original Message----- From: firstname.lastname@example.org [mailto:email@example.com] On Behalf Of Pasi Ojala Sent: Saturday, April 07, 2007 4:22 PM To: firstname.lastname@example.org Subject: Re: Commodore joystick ports > basically PWMs 5volts into the charge line, while watching > the line for the clamp to 0 volts. You are right, I reread the POT subsection from the Programmer's Reference Guide and it seems my recollection has been spoiled by the little ADC knowledge I have gotten much later. The SID ADC is much simpler than I remembered. So, something like this happens: 1) every 512 clock cycles SID will ground the POTX/POTY inputs, thus emptying any charge accumulated into the external capacitor. 2) then an external voltage source (+5V) will start to recharge the capacitor(s) through an external series resistor (the paddle potentiometer) 3) when the voltage potential of the capacitor reaches a "decision level", the time elapsed will be the conversion result. Does anyone know if the POTX/POTY are multiplexed to use the same counter, or why is that 512 cycles instead of 256? I am also no analog expert by any means, but it still seems to me that it would be possible to simply use a series resistor to convert the external voltage level into a current. When used "normally", the voltage is constant and the resistance changes, changing the current that charges the capacitor. If the voltage changes, but the resistance remains the same, the current that charges the capacitor changes. Both cases should seem about the same to the capacitor.. -Pasi -- /She was not one of those fool women who tossed their brains at a man's feet along with their hearts. It was just that sometimes, near him, thinking clearly became a trifle difficult. That was all./ -- Min in The Wheel of Time:"A Crown of Swords" Message was sent through the cbm-hackers mailing list Message was sent through the cbm-hackers mailing list
Archive generated by hypermail pre-2.1.8.