Re: Commodore joystick ports

From: Jim Brain (
Date: 2007-04-08 22:43:08

Scott McDonnell wrote:
> Pasi,
> 512 cycles, because of the nyquist rate (at least 2x the max desired
> sample frequency), perhaps?
Since I've already put a disclaimer out on my analog skills, I don't 
believe that is the reason, since the ADC in the SID was not designed to 
measure waveforms, just a static load.

Based on testing, they do not appear to be multiplexed.  I base that on 
placing two 10K resistors from 5volts (pin 7) to both POT lines.  The 
scope shows the drive to 0v happens at the same exact moment.


"These pins are inputs to the A/D converters used to digitize the 
position of potentiometers. The conversion process is based on the time 
constant of a capacitor tied from the POT pin to ground, charged by a 
potentiometer tied from the POT pin to +5 volts. The component values 
are determined by:

R*C = 4.7E-4

Where R is the maximum resistance of the pot and C is the capacitor. The 
larger the capacitor, the smaller the POT value jitter. The recommended 
values for R and C are 470 kOhm and 1000 pF. Note that a separate pot 
and cap are required for each POT pin. "

If I disconnect the 10K from one POT line 1.0volt is still charged onto 
the cap.  The discharge time goes down quite a bit, but it's still 1uS 
or so.

I'm struggling with the note above about measuring the discharge time.  
Based on my notes, and allowing for the error introduced by using the 
scope, the difference between a reading of 10 and 255 is 1uS, far too 
small a time constant for the 64 to measure, no matter which clock you 
used for the counter.

Jeri should chime in, since she re-implemented the SID POTs for the DTV, 
but based on more testing, I'm going to go with the following theory

SID contains 1 9 bit counter, and 2 2volt comparators.  9th bit is 
hooked to 2 transistors that clamp input POT lines to ground.
At time 0, SID releases the POT line from ground and starts counting.  
the internal comparator latches the current counter value (lower 8 bits) 
into the appropriate POT register when 2 volts is reached.
At time 256, the 9th bit goes high, clamping the line to 0. 
the cycle repeats. (the comparator is still active, but the line will 
never reach 2.0v, so the value is never latched into the SID register.)
At time 512, the counter rolls over, 9th bit goes low, releasing the POT 
line and the process repeats.

I am pretty sure everything but the part in parens is correct.  I 
connected a paddle and tried it out, while watching the scope.  The 
reading was 255 until the charge cycle hit 2 volts.  By varying the 
charge cycle to hit 2v at time 128 (0 being unclamping of the line), the 
POT register read 128 (or so).  From the scope:

(caclulated value in parens)

2v at 100% = 255  (255)
80%=210   (204)
75%=189   (191)
60%=153   (153)
50%=130   (127)
40%=104   (101)
20%=54   (51)
0%=4   (0)

My statement in parens in the description is based on CBM designers 
being typically thrifty.  I can see them implementing a 9 bit counter, 
using the high FF to switch a transistor that would drive the POT line 
to ground, but not bother with bypassing the comparator (since it would 
never get triggered).

The thrifty rationale is how I explain the 512 cycle period.  Since it 
would have taken 2-5uS to completely discharge the cap, they'd need to 
wait that long (or a bit longer) before unclamping the line and starting 
the counter.  That would mean another counter, or a check of 261 (256 
line + 5 or so) on the counter (more gates), and then more gates to 
reset the counter.  Since the POT lines were assumed to be DC (no 
periodic waveforms), letting the counter simply roll over used the least 
gates for the task at hand.

It piqued my interest, but I fear I've exhausted my free time to 
research this.  Hopefully others can add more light to the mystery.

FWIW, the AVR code I use to simulate the paddles is at


Jim Brain, Brain Innovations                                      (X) 
Dabbling in WWW, Embedded Systems, Old CBM computers, and Good Times! 

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