From: john/lori (lgnjh_at_earthlink.net)
Date: 2007-04-08 09:51:26
Scott McDonnell wrote: > 512 cycles, because of the nyquist rate (at least 2x the max desired > sample frequency), perhaps? I always assumed it was for simplicity. You need an 8 bit counter for the ADC, they just added a bit as a simple way to control the timing of the discharge and make sure it lasts long enough to fully discharge. > Yep, this is how I remember it working. I was using a 555 timer and a > counter to emulate the SID pot inputs. I believe this is method is > called a "dual slope integrating ADC." RC time constants are very > predictable. The SID ADC is a single slope integrator. > The only reason I still hold some doubt about this is that the paddles > use 5V, the resistor changes the amount of time it takes for the cap to > reach 63% of 5V. If you input say 2V, it will never reach 63% of 5V. The > resistor never changes the voltage, just the current (or charge rate of > the cap.) So the "decision level" you mention below would never really be satisfied. Which is the beauty of Jim Brains (or whomever's) scheme. I think you could probably even rig a 555 one shot so that it was synced as Jim does. But even a free running oscillator (be it pwm or pulse posistion) should work if it's running fast enough. Message was sent through the cbm-hackers mailing list
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