From: Jim Brain (brain_at_jbrain.com)
Date: 2004-11-03 19:46:10
I like the idea, but I'm struggling with an issue The plan: Set timer1 to Normal (non-PWM) mode, (output disabled), then let the timer run at CLK speed. bring pins high or HiZ When falling edge on POT happens, AVR will latch timer1 and generate IRQ In ISR, read ICP match. Add 8(256 + x) and store in OCR1A, 8(256+ y) to OCR1B. Set both pins low and turn on toggle on match output mode do other work The problem I see with this: If the next IRQ does not happen before the timer makes a full run around (say the application switches to the other joyport, which means I get disconnected from SID), the pins will toggle low again, and I may miss an IRQ (I cannot detect the IRQ while the pins are low.) To get around this, I thought about enabling the OCR IRQs. When they are triggered, depending on which (x or y) is bigger, turn on the overflow IRQ. In the overflow IRQ, set pins to high and turn off toggle on match mode. I *think* that may work, but I'm going to save my current code, which is a lot simpler. Before the scope arrived, I'd dare not try such a complex algorithm, but I'll try it because: a) I already have some code working b) I can see what is going on now on the wire much better than last time. If this works, and I can use the ICP IRQ as my trigger IRQ, then I might be able to go back to using the Tiny28, which was my original target. That part is smaller, cheaper, and seems a good fit for this use. The Mega8 is oversize, but I needed the SPI, given that my bit-bang SPI-like solution was stopping when the POT code was running. It also means I'd have a rock-stable POT emulation, which would be nice. Of course, if the above works, it means my IRQ code does NOT need to be synchronized, as the only time I change pins states is at the beginning of the cycle, and the SID is clamping the cap during that time, so delay is not a big deal. I wonder why they felt the need to discharge the cap for 256 cycles. It seems like it would lose charge after just a few. Jim -- Jim Brain email@example.com Message was sent through the cbm-hackers mailing list
Archive generated by hypermail pre-2.1.8.