RE: 6510 CPU extensions - RAMs

From: Gideon Zweijtzer (
Date: 2002-05-02 13:11:15

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    |> Hmmm, wait a minute..... Not a good idea afterall: this would mean that
    |> SDRAM is occupied at least 50% of the time only because the VIC needs to
    |> read data. (or can you circumvent this, Gideon ???)
    |Since the VIC does only need 8 bit data being fetched/present during that
    |time, why not wasting 8 (internal) flipflops on them... That way the SDRAM
    |would only be occupied the minimum possible time where VIC can be as slow
    |as it wants to.
    Yes, using a read-buffer (one byte deep) already gives a great performance
    gain. A read-buffer of four-deep (to match the 32 bit SDRAM width) would
    even be better. Most VIC accesses are sequential anyway.
    So in other words: Whether we use TRUE dpram or we implement pseudo dpram
    (which has a VIC port that maps to the SDRAM), the solution of replacing the
    on board memory is always faster that queuing the writes to video-memory
    into the on board DRAMs.
    IMHO it IS possible to get the VIC address out of the expansion port, so if
    we disable or remove the DRAMs from the main board, we can actually provide
    the VIC with the right videodata through the expansion port.
    Does anyone know if A14 and A15 on the expansion connector also represent
    the state of the CIA bank select signals during the VIC access phase?
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