RE: 6510 CPU extensions - RAMs
Date: 2002-05-02 12:07:26

  • Next message: Rainer Buchty: "RE: 6510 CPU extensions - RAMs"
    Hallo Gideon,
    > > How about disabling the output enable of the internal
    > > DRAMs and putting this DPRAM on an expansion board, so
    > > the VIC can read its data through the expansion port?
    > > (I think the demultiplexed address is  available as
    > > well, in order to be able to access the CHAR ROM.)
    Yes and no. Only A0..A7 are available, A8..A11 are generated by the VIC. But
    IMHO these lines don't represent the value towards the DRAMs when CAS = (L).
    > Well... I think we need to remove the original DRAMs and
    > then put the dual port ram.... it means we need to hack
    > the C64 main board.
    No dual port RAMs. But for the rest this is indeed a good idea: remove the
    DRAMS and connect all involved signals directly to the FPGA: CAS, RAS, WE,
    Do/Di, A0..A7. 
    > 2 HC574 or HC374 buffers for the address lines and some TTL 
    > logic. Not too complex.
    This is something the FPGA can do (better).
    Especially for Gideon: In this way we don't need to specify what range is 1
    MHz and what range is not.
    Hmmm, wait a minute..... Not a good idea afterall: this would mean that the
    SDRAM is occupied at least 50% of the time only because the VIC needs to
    read data. (or can you circumvent this, Gideon ???)
    Don't know DPRAM good enough: can one system read/write data from one port
    when the other system is reading from it? If not then we have the same time
    If yes, my second thougth, especially for Gideon: when using DPRAM, we still
    need the MMU mechanism. So is the effort, using DPRAM, worth the gain in
       / __|__
      / /  |_/     Groetjes, Ruud
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