From: Jozsef Laszlo (laszloj_at_psi.com)
Date: 2002-05-02 10:22:39
> read two bytes in one clock cycle, but of course only from the same column > or row (I also mix these up..) > > Static RAMs also have their pitfalls. Some brands do not allow the address > to change during a read cycle (CS and OE active) but want the CS or OE to > toggle to go to the new address. It is especially nasty in designs that want > to do an access in every clock cycle (need to "or" the chipselect with the > clock to make 'half' cycles! Yuck) > > Synchronous SRAM is quite interesting, too ;) Hi, Sorry guys, probably I missed the beginning of this discussion but there is an idea... what about multiport static rams? These rams has two separated address/data/control port so it's possible to access them with two devices. One is the VIC chip (here of course we need to "convert" the DRAM address lines into normal static address.. but it's possible), and the other device is the CPU/system. Have a look at it: http://www.idt.com/products/pages/Multi-Ports.html Though these rams still have this "busy" state, I guess it's really easy to implement, cause this line should be connected to the RDY, WAIT whatever. The access time is 15-20 ns... which seems fast enough. What do you think? cheers Jozsef Message was sent through the cbm-hackers mailing list
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