RE: Logic analyzer (Was: 6510 in FPGA works!!)

From: Gideon Zweijtzer (
Date: 2002-04-18 07:48:23

  • Next message: Spiro Trikaliotis: "OT - limitation of PC's parallel port (was: Logic analyzer)"
    >ST> Thus, you would have a very simple digital analyzer with a
    >ST> resolution of about 250 kHz. Is this enough?
    >I'm looking for something that could at least snoop the databus in the
    >C64, so I guess not.
    Hi :)
    I once made a simple 'logic analyzer' that monitors 16 pins and runs at
    maximum of 40 or 50 MHz, so you have 25 or 20 ns resolution. What I did was
    checking for changes of the signal levels and only storing the changes
    together with a 16-bit timestamp, using a non-linear timer (the longer it
    takes, the slower it counts). This enables you to capture only the data of
    interest with the resolution of interest. The 32-bit (16 for the signals and
    16 for the timestamp) 'events' could then be read out through a serial port
    at 115k2.
    I used a very small fpga for this, plus a cheap external sram; like the
    628256 (128Kx8), plus of course a MAX232 and a crystal oscillator. All
    together maybe something like 50 euro.
    There are some limitations however; if there are too many consecutive
    changes at maximum resulution (25 ns), it will have an overrun of the
    internal FIFO, since it only holds 256 entries. This FIFO is used to write
    the events to a slower SRAM (only 8 bits wide and 70-100 ns), so you can
    capture more than just the 256 entries that can be stored in the fpga
    With regards,
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