Re: VHDL description of the REC

From: john/lori (
Date: 2001-09-19 22:09:05

After a cursory look (and a few passes with the Xilinx syntax checker),
I think it needs some work.

I am no VHDL guru.

You start by making a component instantiation of an entity you
haven't defined yet.

aec is defined but not used
ba is defined twice (once as IO)
ip, eob, fault are defined as vectors (but not constrained)
state is defined as a 4 bit vector, (3 downto 0) (should be (2 downto
reload is not defined
Xilinx at least, wants rising_edge(), falling_edge() (not rising'edge(),
falling'edge() )

I think you've got too many elseif's in the "DMA transfer" (?)

if rst='0' then
elsif rising'edge(dotclk) then
elsif falling'edge(dotclk) then

That's as far as I've gotten

I don't think there's any such thing as too many comments.


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