Re: 6522 VIA Questions

From: Ojala Pasi 'Albert' (
Date: 2001-08-29 09:24:42

> >positive half of PHI2. The trick is to slow down the rising edge of PHI2
> >using the DOT-clock. Connect the DOT-clock to the CLK-input of a 74,
> This explains why my attempts to interface an LCD controller directly to the
> bus using the 6502 method in the datasheets was such a failure :(

I used a simpler method of combining PHI2 and _I/Ox to make a latch
enable signal when I made a 256kB RAM expansion ~15 years ago.

"Mythology -- those times when I was alive. When I could still see the sun.
 But in this mythology is rooted all the truths that I know. And if we go
 back, we can find the future, and the means to change it. The very least
 we can do is seek to understand." -- Maharet in "The Queen of the Damned"

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