> But is the swap operation really different from the other three operations > (C64->REU, REU->C64, compare REU==C64)? The operation takes 2 bus clock > cycles per byte, unlike the other operations which require one cycle per > byte. In my opinion, the only difference is that you need to buffer two > bytes between the memory access cycles instead of one. The problem comes indeed from DRAM addressing. Doing it the conventional way it looks like that: apply row address apply RAS apply column address apply CAS read/write data (strobe WR) release CAS/RAS Where you can mix the C64 access into these on memory transfer you have to apply another write data/strobe wr cycle on swap operation. Also, you need to do the DRAM refresh some time. Either by just reading every address like the VIC does (hoping that 2^24 cells will hold their data) or doing a CBR. > Me too. Do you know if the tools are freely available? I like the Atmel > AVR family of microcontrollers, because everything can be done with free > software. I use the avra assembler and the uisp programmer. Yes, the Xilinx WebpackISE software is freely downloadable after registration. Runs under Windows only, though. For CPLD design you don't even more software than a web browser and a text editor due to their WebFitter (which basically looks like a webalized MINC software to me). Rainer -- Rainer Buchty, LRR, Technical University of Munich Phone: +49 89 289-28401, Fax +49 89 289-28232, Room S3240 Message was sent through the cbm-hackers mailing list
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