Rainer Buchty wrote: > > The problem comes indeed from DRAM addressing. Doing it the conventional > way it looks like that: > > apply row address > apply RAS > apply column address > apply CAS > read/write data > (strobe WR) > release CAS/RAS > Has anyone considered using P-SRAM (pseudo-static RAM)? I don't have any experience from using those myself, but I guess this would greatly simplify the addressing and refresh issues. -- Christer Palm Message was sent through the cbm-hackers mailing list
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