Re: IRQ for 6502

From: Marko Mäkelä (msmakela_at_cc.hut.fi)
Date: 2001-08-21 10:37:36

On Tue, 21 Aug 2001, Christer Palm wrote:

> However, I'm a little curious about the specific case I describe (i.e.
> executing an RTI while the IRQ signal is active all along). Since RTI
> pulls P before PCL and PCH the interrupt condition should indeed be met
> 2 cycles before the RTI ends, which would, according to your rule, mean
> that the IRQ would indeed be taken immediately after the RTI. I
> interpret your response as if it isn't - why is that? (haven't tried it
> myself, although this of course extremely easy to test.)

I'm not sure if I have measured the RTI instruction, and my measurements
on the other instructions are from 1996 or earlier.  I really don't
remember.  But it's not too hard to measure these yourself: just write
some 100% accurately timed interrupt routines so that you can predict
exactly when the next interrupt occurs.  In the interrupt routine, store
or display the return address (or just some of its low-order bits) in some
way.  Make sure that the start of the interrupt routine always takes the
same number of cycles.  Add a parameterized delay before the RTI, CLI or
PLP instruction.  You don't have to RTI from the interrupt; stack
overflows don't cause any trouble if you know what you are doing.

> The reason I'm curious is that I have a half-finished VHDL model of the
> 6502 in my "unfinished projects drawer" which was indended to be a cycle
> exact 6502 clone, however I never got around to explore the innards of
> the interrupt logic. Would be fun to finish that part too someday.

It would be interesting to see how much you can minimize the port
equations.  I suspect that the undocumented opcodes are byproducts,
unlike the undocumented opcodes of the Hitachi 6309 (a Motorola 6809
clone), which were implemented on purpose.

Speaking of VHDL, I had a quick look at the 16 MB SDRAM chip data sheet.
Its interface looks pretty complex.  This probably is the reason why the
manufacturer supplies simulation models and a VHDL description of the
chip.

	Marko


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