Re: IRQ for 6502

From: Christer Palm (
Date: 2001-08-21 15:07:12

Marko Mäkelä wrote:
> I'm not sure if I have measured the RTI instruction, and my measurements
> on the other instructions are from 1996 or earlier.  I really don't
> remember.  But it's not too hard to measure these yourself:
> ...

He he, I actually had a much simpler method in mind for this specific
case. Just write a loop doing INC $D020 or something, then ground the
IRQ signal.

> It would be interesting to see how much you can minimize the port
> equations.  I suspect that the undocumented opcodes are byproducts,
> unlike the undocumented opcodes of the Hitachi 6309 (a Motorola 6809
> clone), which were implemented on purpose.

Knowing your undocumented 6502 opcodes is actually the key to
understanding a lot of the instruction decode logic and the ALU. There
is no question that they are byproducts.

Ironically, one could expect a "hardwired" design like the 6502 to use
some extremely clever instruction decode logic, but this seems not to be
the case. I guess there's a limit on how clever one can be with only 8
bits of opcode at hand :-). I understand that another probable reason is
that you can rely heavily on wire-OR in NMOS logic.

Another truly interesting artifact are the read-modify-write (xxxxxx10)
instructions (ASL, ROL, LSR, ROR, DEC, INC). There seems to be no good
reason to why these instructions does not have the Indirect Indexed,
Indexed Indirect and Absolute Indexed Y addressing modes.

Also the logic that decodes some of the Implied instructions (TAX, TXA,
DEX, etc.) stomps on the quite useful DEC A and INC A instructions.

Etc, etc... there are quite a few things like that. Seems like Peddle &
co were in quite a hurry when doing the design.

> Speaking of VHDL, I had a quick look at the 16 MB SDRAM chip data sheet.
> Its interface looks pretty complex.  This probably is the reason why the
> manufacturer supplies simulation models and a VHDL description of the
> chip.

Yeah, also, almost every reasonably complex logic design is done in VHDL
(or VERILOG) today and put into an ASIC or FPGA (which is a truly
revolutionizing invention). It's always nice to have ready-made models
of the chips you'd use around it so you can simulate the whole design
without having to write your own sim models. So I think we will see this
more and more.

While on the topic of VHDL, I personally believe that it's kind of
awkward to use a language that stems from ADA, which is procedural, to
describe logic state. One would expect something more like Prolog.

On the other hand, it's kind of cool with a language where all your
loops executes all iterations simultaneously at almost infinite speed.
Sounds like science fiction :-)

Christer Palm

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