Marko Mäkelä wrote:
>
> On Mon, 20 Aug 2001, Christer Palm wrote:
>
> > Similarly, if you forget to clear an IRQ condition inside an interrupt
> > handler by doing whatever is needed to clear it, the interrupt would
> > immediately occur again when you return from the interrupt handler and
> > the RTI re-enables the interrupts.
>
> A minor correction that may make a major difference when the timing is
> tight: the interrupt cannot occur immediately after the instruction that
> cleared the Interrupt flag (RTI, CLI or PLP), but after the following
> instruction. Due to the instruction pipeline in the 6502, the interrupt
> condition must be enabled 2 cycles before the end of the currently
> executing instruction in order for the interrupt to be taken. I haven't
> seen this documented anywhere, but I've measured this on the C64.
>
I assume that you are correct, Marko!
However, I'm a little curious about the specific case I describe (i.e.
executing an RTI while the IRQ signal is active all along). Since RTI
pulls P before PCL and PCH the interrupt condition should indeed be met
2 cycles before the RTI ends, which would, according to your rule, mean
that the IRQ would indeed be taken immediately after the RTI. I
interpret your response as if it isn't - why is that? (haven't tried it
myself, although this of course extremely easy to test.)
The reason I'm curious is that I have a half-finished VHDL model of the
6502 in my "unfinished projects drawer" which was indended to be a cycle
exact 6502 clone, however I never got around to explore the innards of
the interrupt logic. Would be fun to finish that part too someday.
--
Christer Palm
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