On Mon, 20 Aug 2001, Christer Palm wrote: > Similarly, if you forget to clear an IRQ condition inside an interrupt > handler by doing whatever is needed to clear it, the interrupt would > immediately occur again when you return from the interrupt handler and > the RTI re-enables the interrupts. A minor correction that may make a major difference when the timing is tight: the interrupt cannot occur immediately after the instruction that cleared the Interrupt flag (RTI, CLI or PLP), but after the following instruction. Due to the instruction pipeline in the 6502, the interrupt condition must be enabled 2 cycles before the end of the currently executing instruction in order for the interrupt to be taken. I haven't seen this documented anywhere, but I've measured this on the C64. Marko Message was sent through the cbm-hackers mailing list
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